Strobe-based data signaling is common in many memory systems, such as “Double Data Rate Synchronous DRAM” (DDR-SDRAM) and its related variants. In such systems, reception or sampling of data under control of a strobe signal involves use of the strobe signal to generate sample clock signals that control sampling instants of a receiver associated with a data line or pin of the memory component. Once the data transmitted by the DRAM during a “read” operation (i.e., the read-data) is sampled by the receiver circuitry on the memory controller, that data must be reliably transferred into the core of the memory controller, for continued processing. While the core-clock of the memory controller and the clock of the memory channel are typically the same frequency, the arriving data-strobe signal is of arbitrary phase with respect to the core-clock of the memory controller.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 100 is first introduced and discussed with respect to FIG. 1).